This section is intended to introduce the reader to aspects of the art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
The increased speed and capability of computers has had an enormous impact on our society. The Internet, advanced software applications, speed recognition, advances and telecommunications and the many other high speed applications are made feasible only because the performance of silicon-based integrated circuit devices has increased over time. As can be appreciated, faster performance is generally desirable.
Current integrated circuit devices, such as metal oxide semiconductor (MOS) transistors, are limited by constraints inherent in existing silicon technology. For decades, scientists have been searching for ways to enhance existing silicon technology to speed computer performance. As can be appreciated, any medium that can conduct electricity has some degree of capacitance associated therewith. Technically, a MOS transistor is regarded as a capacitive circuit. This implies that the MOS circuit must completely charge to full capacitance to activate its switching capability. The process of discharging and recharging the transistor requires a relatively long amount of time when compared to the time it requires to actually switch the voltage state of the transistor's metal layer. The “junction capacitance” of a transistor generally refers to the charge-storing area between the impurities added to a chip's silicon and the impurity-free silicon substrate. Reducing the junction capacitance associated with the transistor will enhance performance of the device by increasing the operating speed.
Silicon-on-insulator (SOI) is a relatively new technology that offers certain advantages over prior techniques. SOI differs from CMOS by placing the transistor's silicon junction area on top of an electrical insulator. The most common insulators employed with this technique are glass and silicon oxide. By placing a thin layer of insulator between the impurities and the silicon substrate, the junction capacitance is greatly reduced or eliminated, thereby enabling the transistor to operate faster. As transistor latency drops, the ability to process more instructions in a given time increases and overall system performance is positively impacted.
Though SOI technology offers certain advantages over existing silicon technology, further size reduction and cost reduction may be desirable. Further, devices having lower leakage currents and stable refresh rates is also desirable. As can be appreciated, improved manufacturability is often desirable, as well.